It is desirable to be able to adjust the performance of semiconductor integrated circuits after processing has been completed to minimize variations associated with process tolerances.
For example, in many semiconductor devices minimum timing requirements need to be maintained for proper operation. These timing requirements are generally based on an external clock or on internal delay elements.
Even when the timing requirements can be accurately modeled in simulation, it will differ from chip to chip due to process differences and will also differ over the temperature and voltage range allowed by the specification. The optimization of yield and performance of such devices requires a chip by chip adjustment of the delay circuits. However, optimization should be performed in a production environment that tests a multitude of chips in parallel in order to reduce test time and cost.